1. Field of the Invention
The present invention relates to a method for generating dummy patterns between the interconnection wiring patterns and extracting LCR in a design process of semiconductor integrated circuits (referred to as LSI hereinbelow) and to a computer program for execution thereof with a computer, and more particularly to an LSI design method which makes it possible to decrease a pattern density degree variation in the wiring layer and simplify the LCR extraction process and to a computer program therefor.
2. Description of the Related Art
An LSI design process is usually conducted by CAD with a computer. The LSI design process comprises a logic design process for designing a logic circuit by connecting the logic gates, a layout design process for laying out the logic circuit on a chip, a process for extracting the LCR (inductance, capacitance, resistance) of the laid-out interconnection wiring from the layout data, and for finding the signal path delay time from the extracted LCR values and AC characteristic of cells or macros, a logic simulation process for checking whether the logic circuit operates normally by using the delay time, and a physical inspection process for checking whether the layout data satisfy the design rule.
The layout design creates layout data containing wiring pattern data of each layer on the chip. The values of LCR of the interconnection wiring patterns are extracted based on the layout data. The LCR extraction process, delay time calculation process, and logic simulation process are usually provided in a single program module.
In the LCR extraction process, the resistance R, capacitance C, and inductance L are extracted by computation or by referring to a parameter table according to the wiring width, distance between the adjacent wirings or overlapping surface area contained in the layout table.
In the LCR extraction process, the distance to the adjacent interconnection wirings in the same wiring layer is extracted with respect to the object interconnection wiring, the capacitance value C corresponding to this distance is extracted, and the capacitance value corresponding to the adjacent interconnection wirings in different wiring layers is also extracted by referring to the layout data. Therefore, the LCR extraction process requires data processing with a comparatively heavy load.
On the other hand, due to recent pattern miniaturization, the width of the actually formed wiring pattern becomes different from the width of the wiring pattern in the layout data under the effect of fabrication processes. Etching of interconnection wiring patterns is one of the fabrication processes which apparently affects the wiring pattern width. In a reactive ion etching (RIE) process in which a reaction gas is introduced into a high-vacuum atmosphere, plasma is generated by applying a high frequency, and a wiring layer such as aluminum layer is etched, a pattern width variation effect can be observed in which the pattern width is decreased or increased due to the pattern miniaturization. Such changes in the pattern width caused by etching are generated in response to the degree of pattern density. Therefore, it is desired that the variations of the density degree be kept as small as possible.
A method of inserting a dummy pattern, which is not connected to any wiring pattern, in a region in which the distance between the wiring patterns is large, is used to decrease the variation of the pattern density degree in a wiring layer. However, because of the generation of dummy patterns, the extraction and computation of values of capacitance between the wiring layers become complex and the correct capacitance values are difficult to extract by simple data processing.
Accordingly, it is an object of the present invention to provide an LSI design method which can generate a dummy pattern without complicating the LCR extraction process and a computer program therefor.
Another object of the present invention is to provide a dummy pattern generation method which simplifies the LCR extraction process and a computer program therefor.
In order to attain the above-described object, in accordance with the first aspect of the present invention, conductive dummy patterns continuous in a direction perpendicular to adjacent wiring patterns are inserted at a first distance from the adjacent wiring patterns between the adjacent wiring patterns extending in one direction, in an interconnection wiring layer in an LSI. The insertion of such dummy patterns makes it possible to suppress variations in the degree of pattern density in the interconnection wiring layer and suppress variations in the pattern width in the etching process. Furthermore, since the conductive dummy patterns are continuous in the direction perpendicular to the adjacent wiring patterns, the values of capacitance between the adjacent wiring patterns in the same wiring layer assume a constant value corresponding to the first distance, regardless of the distance between the adjacent wiring patterns. Therefore, even in the case of different distances between the adjacent wiring patterns, the value of capacitance between the adjacent wiring patterns can be extracted as a constant value and the process for extracting the capacitance value C in the LCR extraction process is simplified.
In the preferred embodiment of the present invention, dummy patterns are generated over the entire surface in the interconnection wiring layer and then the dummy patterns present in the region within the first distance from the wiring patterns are removed. With such method, if the distance between the adjacent wiring patterns is confirmed to be no less than the doubled first distance, the dummy patterns separated form the wiring pattern by the first distance can be automatically generated without detecting the distance between the adjacent wiring patterns.
In another preferred embodiment of the present invention, the characteristic of capacitance between the adjacent wiring patterns comprises a first region where the value of capacitance between the adjacent wiring patterns greatly changes in response to changes in the distance of a dielectric between the adjacent wiring patterns and a second region where those changes are less than in the first region, and the first distance is selected as a minimum distance (strictly speaking, xc2xd of the minimum distance) in the second region.
By selecting the first distance between the wiring patterns and dummy patterns as a minimum distance (strictly speaking, xc2xd of the minimum distance) in the second region, it is possible to make the value of capacitance between the adjacent wiring patterns as small as possible and also to expand as much as possible the region where the degree of pattern density in the interconnection wiring layer is constant.
In another preferred embodiment of the present invention, the characteristic of capacitance between the adjacent wiring patterns comprises a first region where the value of capacitance between the adjacent wiring patterns greatly changes in response to changes in the distance of a dielectric between the adjacent wiring patterns and a second region where those changes are less than in the first region, and the first distance is selected as a predetermined distance (strictly speaking, xc2xd of the predetermined distance) in the first region.
When the distance between the adjacent wiring patterns is shorter than the minimum distance in the second region, the distance between the wiring patterns and dummy patterns is selected as a predetermined distance in the first region. As a result, because of the generation of dummy patterns, the value of capacitance between the adjacent wiring patterns can be made constant and the LCR extraction pattern can be simplified even when the distance between the adjacent wiring patterns is comparatively short.
In order to attain the above-described object, in accordance with the second aspect of the present invention, an LSI design method including a formation of wiring patterns in an interconnection wiring layer is provided, this method comprising:
a layout process for forming wiring patterns in the interconnection wiring layer from logic data containing a plurality of cells and connections thereof;
a dummy pattern generation process for inserting conductive dummy patterns continuous in the direction perpendicular to the wiring patterns between the wiring patterns, which are adjacent and extend in the same direction, at a first distance from the adjacent wiring patterns; and
a capacitance extraction process for extracting a value of capacitance between the adjacent wiring patterns where the dummy pattern is generated as a capacitance value corresponding to the first distance.